1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a nonvolatile memory transistor composed of a floating gate type field effect transistor, and a method of manufacturing the same.
2. Description of the Related Prior Art
Hitherto is known a nonvolatile memory transistor composed of a floating gate type field effect transistor capable of writing and erasing by tunnel injection and tunneling erasure as one of the nonvolatile memory devices capable of writing and erasing electrically.
It is the principle of the nonvolatile memory transistor having the floating gate to vary the threshold voltage of the transistor and store the information, by tunnel injection of electric charge from the semiconductor substrate side through a thin dielectric film, or extracting the electric charge from the floating gate electrode side through the thin dielectric film, thereby changing the electric charge accumulated on the floating gate electrode on the dielectric film.
In case of using the nonvolatile memory transistor of the floating gate type in a semiconductor integrated circuit such as EEPROM (electrically erasable and programmable ROM), generally, in order to prevent excessive erasure when erasing, that is, to prevent the channel region beneath the floating gate electrode from being always in ON state due to excessive removal of electrons from the floating gate electrode, an offset region is provided, which can be controlled directly by a control gate electrode without being covered with the floating gate electrode.
Therefore, a conventional semiconductor memory device has such a sectional structure as shown in FIG. 20.
Herein, the region in which the thin silicon oxide film 4 is formed is generally formed by photolithography. That is, only the resist on the region formed the thin silicon oxide film 4 is removed, and the silicon oxide film 5 is removed using the resist as the mask. Afterwards, removing the resist and oxidizing again, a thin silicon oxide film 4 is formed.
In the conventional structure, the N type diffusion layer 2 formed in the substrate beneath the thin silicon oxide film 4 and the N type diffusion layer 3 corresponding to the drain of the memory cell must be electrically connected with each other. Besides, for stabilizing the writing characteristics of the semiconductor memory device, the region formed the thin silicon oxide film 4 must be formed so as not to be larger than the floating gage electrode 6 to be formed later.
In the conventional memory cell structure, since the size of the tunneling region is defined by the mask, it is difficult to reduce the size of the tunneling region itself. It is also necessary to obtain a sufficient alignment margin for the tunneling region and the floating gate electrode 6, and hence it is difficult to reduce the cell size, too. Still more, in the conventional memory cell structure, it is required to connect the N type diffusion layer 9 beneath the tunneling region and the N type diffusion layer 3 diffused by self-alignment from the end of the floating gate electrode 6 and the end of the control gate electrode 8, or to form a combined shape of the N type diffusion layer 9 beneath the tunneling region and the N type diffusion layer 3 diffused by self-alignment from the end of the floating gate electrode 6 and the end of the control gate electrode 8, preliminarily before forming the floating gate electrode 6. In the former case, the manufacturing process is complicated, and in the latter case, it is disadvantageous for reducing the memory cell because the one N type diffusion layer of the memory cell cannot be formed by self-alignment with the floating gate electrode.